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new product r03ds0012ej0100 rev.1.00 2011.09.05 page 1 of 10 r03ds0012ej0100 rev.1.00 2011.09.05 8-bit i/o expander for i 2 c bus (corresponds to fast mode) R2A20150NP/sa description features application block diagram scl sda i 2 c bus transciever 1 d0d1d2d3d4d5d6 shift resistor 8 so d7 i/o port 8 8 v dd gnd output data 8 input data input/output output data latch 8 8 i/o setting data latch input data latch cs2 cs1 cs0 power on reset reset the R2A20150NP/sa is a cmos 8-bit i/o expander, which has serial to parallel and parallel to serial data converting functions. it can communicate with a microcontroller via few wiring thanks to the adoption of the 2-wire i 2 c bus. maximum 8 ics can be connected to a bus by using 3-chip select pins, so that it is possible to handle up to 64 bits data. ? simple 2-wire (scl and sda) communication with a microcontroller. ? 8-bit data conversion between serial and parallel by i 2 c bus. ? corresponds to fast mode (400khz) of i 2 c bus specification. ? possible to set input and output each bit separately. ? by using three chip select pins (cs0,cs1,cs2), r2a20150 can connect with the same bus line to maximum 8 pieces. ? very small package line-up qfn-16 and tssop-16. number for tssop package number for qfn package i/o port expansion of microcomputer. data conversion from serial to parallel and from parallel to serial in peripheral of microcomputer. 15 12 13 16 1 14 11 6 10 9 8 7 5 4 3 2 14 15 16 2 3 13 8 12 11 10 9 7 6 5 4
new product R2A20150NP/sa page 2 of 10 r03ds0012ej0100 rev.1.00 2011.09.05 explanation of terminals the pin no. of ( ) are for qfn package qfn tssop 11 14 13 12 10 9 8 7 6 5 4 3 2 1 16 15 chip select data input terminal this ic accessed only when the lower 3bits data from slave address coincide with the data of cs0 to cs2. input cs2 14 cs1 15 cs0 16 serial data output terminal output so 1 gnd terminal - gnd 8 power supply terminal - v dd 13 d7 12 parallel data input/output terminal ( initial state after power on is input mode. ) input/output d6 11 d2 6 d1 5 d0 4 d4 9 d3 7 d5 10 serial data input/output terminal input/output sda 3 serial clock input terminal input scl 2 function i/o symbol pin no. r2a20150sa 1 2 3 4 5 6 7 8 scl sda gnd cs0 cs1 cs2 v dd 16 15 14 13 12 11 10 9 d0 d1 d2 d3 d7 d6 d5 d4 so pin arrangement R2A20150NP (top view) r2a20150sa (top view) 12 11 10 9 1 2 3 4 scl sda d0 d7 d6 d5 d4 package: pwqn0016kb-a [np] d1 d2 d3 gnd v dd cs2 cs1 cs0 5 6 7 8 16 15 14 13 R2A20150NP so package: ptsp0016jb-a [sa]
new product R2A20150NP/sa page 3 of 10 r03ds0012ej0100 rev.1.00 2011.09.05 absolute maximum ratings peak continuous mw/deg 7.25(np) / 3.75(sa) ta> +25deg thermal derating factor k theta ma 0 to +4 -40 to +125 -30 to +85 290(np) / 150(sa) 0 to +30 -5 to 0 -0.3 to v dd +0.3 (<6.5) -0.3 to v dd +0.3 (<6.5) -0.3 to +6.5 ratings ma d0 ~ d7 output current ?low? *1 i ol ma d0 ~ d7 output current ?high? i oh v output voltage v o v supply voltage v dd v input voltage v i mw ta= +85deg power dissipation pd deg storage temperature tstg deg operating temperature range topr unit conditions item symbol recommended operating conditions max typ min unit limits conditions item symbol - - 5.0 0.2v dd v dd 5.5 v 0 input low voltage v il v 0.8v dd input high voltage v ih v 2.7 supply voltage v dd electrical characteristics v 0.2v dd - 0 input low voltage v il s -- 100 v dd =0 to 2.7v supply voltage rise-up time *3 tr vdd v 1.9 1.5 - v dd =0 to 2.7v operating voltage of internal reset *3 v ddpor ms --1 v dd < 0.1v time period of re-power on (power supply off ? on) *3 t por v v dd - v dd ?0.4 i oh =-1ma, v dd =5v output high voltage (d0 ~ d7) v oh v dd - v dd ?0.4 i oh =-500a, v dd =3v v 0.4 - 0 i ol =5ma, v dd =5v output low voltage (d0 ~ d7) v ol 0.4 - 0 i ol =2.5ma, v dd =3v ma - 10 5 v ol =0.4v, v dd =5v output current ?low? *2 (d0 ~ d7) i ol -5 2.5 v ol =0.4v, v dd =3v - 25 15 v ol =1.0v, v dd =5v - 10 5 v ol =1.0v, v dd =3v v- 0.8 0.5 hysteresis of schmitt trigger input (sda, scl) vhys v 0.4 -- isink=3ma output low voltage (sda) v ol v v dd - 0.8v dd input high voltage v ih a 10 0 -10 input leak current i ilk a 10 0.1 - v ih =v dd , v il =gnd, f scl =stop ma 0.5 0.05 - v ih =v dd , v il =gnd, f scl =400khz circuit current i dd max typ min unit limits conditions item symbol *2 : output low current should be set; average current of summary of d0 to d3 or d4 to d7 < 16ma. average current is calculate by below equation; average current = i ol x duty duty : the period of flow i ol (include power off period) *3 : when power supply is turned on, internal circuit is in itialized by power on reset circuit. but, if re-powered on quickly, initialize is not operate. so, keep the time period of re-powered on (t por ). (v dd = +5v +/-10%, gnd=0v, ta= -30 to +85deg unless otherwise noted) v dd internal reset signal t por tr vdd < 0.1v (equivalent to tr vdd ) v ddpor resetting period gnd gnd resetting period *1 : the maximum ratings of output current ?low? is 4ma when using continuously for each port, but peak current is 30ma (13% duty) when considering duty cycle including power off period. (ta= 25 deg unless otherwise noted)
new product R2A20150NP/sa page 4 of 10 r03ds0012ej0100 rev.1.00 2011.09.05 all of above value are corresponds to v ih min and v il max. timing chart sda v ih v il scl v ih v il start start start stop t r , t f t buf t hd:sta t su:dat t hd:dat t su:st0 t low t high tsu: sta c b t su:sto t f t r t su:dat t hd:dat t su:sta t high t low t hd:sta t buf f scl symbol max. min. - 4.0 - - 250 0 4.7 4.0 4.7 4.0 4.7 0 normal mode 400 - 300 1000 - 3.45 - - - - - 100 s - 0.6 set-up time for start condition. only relevant for a repeated start condition. ns 300 - fall time of sda and scl signals s - 0.6 high period of the clock s - 1.3 low period of the clock khz 400 0 scl clock frequency s - 1.3 free time: the bus must be free before a new transmission can start s - 0.6 hold time start condition after this period, the first clock pulse is generated s 0.9 0 data hold time pf 400 - capacitive load of bus line ns 300 - rise time of sda and scl signals s - 0.6 set-up time for stop condition ns - 100 data set-up time max. min. unit fast mode item i 2 c bus characteristics
new product R2A20150NP/sa page 5 of 10 r03ds0012ej0100 rev.1.00 2011.09.05 functional blocks ? i 2 c bus interface the i 2 c bus interface recognizes start/stop conditions, a slave address and a write/read mode selection by receiving sda,scl,cs0,cs1 and cs2 signals and then the latch pulse, dedicated to each data latch are generated. ? data latch this ic has 3 types of data latch: the i/o setting da ta latch, the input data latch and the output data latch and each latch is controlled by the i 2 c bus interface. x i/o setting data latch these latches set input-state or output-state of each parallel data terminals (d0 to d7). they are set at the next byte after receiving the slave address byte in the write mode from the master. in case this latch is set to high, the data is transferred from the i 2 c bus interface to the parallel data terminals. in the opposite transmission: from the parallel data terminals to the i 2 c bus, it is set to low. x output data latch in the write mode, the data from the i 2 c bus to the parallel data terminals is latched. when the master transmits output data after a se tting in write mode, the output data is taken into the latch. x input data latch in the read mode, the data of parallel data terminals is latched in the input data latches. the input data is taken into the latches from the parallel data terminals on every 8th negative edge of scl clock. the latched data is output to the master through the sift resistor. on the output terminal assigned by the i/o setting latch, the input data latc h takes the state of the output terminal. ? parallel input/output port in case i/o setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance and is able to accept an input. in another case i/o setting latch is set to high (output mode), each parallel terminal output a data according to the state of the output data latch. ? serial output port the parallel data from each parallel terminal are conversion to 8bit serial data and output to so terminal. without serial output mode, so terminal goes to low output. ? power on reset when the power is turned on, each latch is reset (i nitialize) and then the parallel data i/o terminals become hi-impedance (input mode).
new product R2A20150NP/sa page 6 of 10 r03ds0012ej0100 rev.1.00 2011.09.05 2.read mode: parallel data input to i 2 c bus data output) (the data transmits continuously each 8bits after se tting slave address. when final data transmitted, do not return the acknowledge, then input the stop condition.) digital data format 1.write mode: i 2 c bus data input to parallel data output (the data transmits continuously each 8bit s after setting slave address and i/o.) transmission from master (mcu etc.) to slave (r2a20150) transmission from slave (r2a20150) to master (mcu etc.) ? s: start condition while scl level is high, sda line level should be changed from high to low. 0 1 1 1 a2a1a0 last first lsb msb note: lower three bits (a0, a1, a2) are a programmable address. this ic is accessed only when the lower 3 bits data of slave address coincide with the data of cso to cs2. (refer to the right table) chip select data ? slave address ? w: write (sda = low), r: read (sda = high) ? a: acknowledge bit (slave side confirm the data receive, change to low in the sda line) *a: in a read mode; after final data transmitted, do not return acknowledge. change to high.) lsb msb (l=low,h=high) ? i/o setting data (i/o setting of parallel data i/o terminals.) note: data input from parallel data terminals = low data output to parallel data terminals = high each bit data corresponds to the i/o st ate of the parallel data terminals. ? p: stop condition while scl level is high, sda level should be changed from low to high. ? 8-bit data ? ? ? ? ? ? lhl010 h l l cs2 hh 111 hl 100 ll 000 cs0 cs1 a0a1a2 p7 p6 p5 p4 p3 p2 p1 p0 first msb last lsb d7 d6 d5 d4 d3 d2 d1 d0 last lsb first msb p 8bit data 8bit data i/o setting w slave address s last first a a a a a pa a a a r slave address s first last 8bit data a 8bit data 8bit data
new product R2A20150NP/sa page 7 of 10 r03ds0012ej0100 rev.1.00 2011.09.05 in a case of a data conversion from serial to parallel transmission from a master (mcu etc.) transmission from a slave (r2a20150) stop condition start condition sda scl d0 to d7 0 1 1 1 a2 a1 a0 0 a p7 p6 p5 p4 p3 p2 p1 p0 a d 1 7 d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 a d 2 7 d 2 6 d 2 5 d 2 4 d 2 3 d 2 2 d 2 1 d 2 0 a 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 hi-z d 1 xd 2 x data output data output slave address i/o setting byte data data all i/o setting resistors are set to low (input) in the write mode, before a parallel data is read. (all i/o setting resistors are set to the input mode after power-on.) sda scl 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 hi-z slave address i/o setting byte 0 1 1 1 a2 a1 a0 0 a p7 p6 p5 p4 p3 p2 p1 p0 a sda scl d0 to d7 input (example) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 d 3 x data latch slave address data data data d 1 xd 2 x d 4 x d0 to d7 output hi-z stop condition functional description all parallel data i/o terminals are set to the input-state after power-on. in case any terminals need to be set to the output state, the corresponding terminals should be set during the write mode. this setting is hold until a next setting. in the write mode, 8 bits data can be transmitted from the i 2 c bus interface to the parallel ports continually after the slave address and i/o setting. in the read mode, 8 bits data can be tr ansmitted from the parallel ports to the i2c bus interface continually after the slave address setting. this 8 bits serial data is output from the so terminal. so terminal sets to ?l? state without read mode. in the case of a changing between the write- and read-mode, the data must be transmitted again from the starting condition. d0 to d7 output so d 1 7 d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0d 3 7 d 3 6 d 3 5 d 3 4 d 3 3 d 3 2 d 3 1 d 3 0 d 4 7 d 4 6 d 4 5 d 4 4 d 4 3 d 4 2 d 4 1 d 4 0 0 1 1 1 a2 a1 a0 1 a d 1 7 d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0a d 3 7 d 3 6 d 3 5 d 3 4 d 3 3 d 3 2 d 3 1 d 3 0 a d 4 7 d 4 6 d 4 5 d 4 4 d 4 3 d 4 2 d 4 1 d 4 0 a in a case of a data conversion from parallel to serial transmission from a master (mcu etc.) transmission from a slave (r2a20150) start condition start condition data latch data latch
new product R2A20150NP/sa page 8 of 10 r03ds0012ej0100 rev.1.00 2011.09.05 an example : the parallel port terminals of d0 to d3 and d4 to d7 are assigned as output and input terminals, respectively. stop condition start condition sda scl d0 to d3 0 1 1 1 a2 a1 a0 0 a p7 p6 p5 p4 p3 p2 p1 p0 a d 1 7 d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 a d 2 7 d 2 6 d 2 5 d 2 4 d 2 3 d 2 2 d 2 1 d 2 0 a 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 hi-z d 1 xd 2 x data output slave address i/o setting byte data data d4 to d7 hi-z * write mode the terminal assigned as an output provides the data written in the output data latch. after power-on, all terminals are reset to the input-state. then an initial data low of the output latch are output after the i/o setting has been done. finally the assigned output are provided after the 8-bit data transmission. then terminal assigned as an input keeps the input condition (high-impedance) regardless of 8-bit data setting. * read mode the input data is taken into input latch on every 8th negative-going edge of the scl clock through the terminal assigned as an input, and then the latched data is output via the sda line. the data of the output assigned terminal is also handled in the same procedures as above. stop condition start condition sda scl d4 to d7 (instance) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 d 3 x data latch slave address data data d 1 xd 2 x d 4 x hi-z d0 to d3 0 1 1 1 a2 a1 a0 1 a d 1 7 d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0a d 3 7 d 3 6 d 3 5 d 3 4 d 3 3 d 3 2 d 3 1 d 3 0 a d 4 7 d 4 6 d 4 5 d 4 4 d 4 3 d 4 2 d 4 1 d 4 0 a d4 to d7 output data so d 1 7 d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0d 3 7 d 3 6 d 3 5 d 3 4 d 3 3 d 3 2 d 3 1 d 3 0 d 4 7 d 4 6 d 4 5 d 4 4 d 4 3 d 4 2 d 4 1 d 4 0 in case the i/o setting is different between each terminals. data output data latch data latch
new product R2A20150NP/sa page 9 of 10 r03ds0012ej0100 rev.1.00 2011.09.05 typical application 10? f parallel input/ output terminal chip select data cs2 cs1 cs0 scl sda v dd gnd d0 d1 d2 d3 d4 d5 d6 d7 so serial data output 11 2 4 13 3 5 4 6 5 7 7 9 8 10 9 11 10 12 15 1 12 14 13 15 14 16 16 2 1 3 mcu 6 8 number for tssop package number for qfn package ordering information embossed taping/2,000 pcs. sa ptsp0016jb-a tssop-16 r2a20150sa embossed taping/3,000 pcs. np pwqn0016kb-a qfn-16 R2A20150NP packing/quantity package type no. package code package name order part no.
new product R2A20150NP/sa page 10 of 10 r03ds0012ej0100 rev.1.00 2011.09.05 package outline np: pwqn0016kb-a sa: ptsp0016jb-a
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